In a multi-chip storage device, a controller located on a first chip may be configured to communicate with a host device, and memory cells storing data may be located on a second chip. When the host wants to read data stored in the memory cells, it may send a host read command to the controller of the first chip, and in turn the controller may retrieve the data from memory cells located on the second chip. Control logic on the second chip may send the data to the controller of the first chip via an external data bus.
For some example configurations, in order for the control logic of the second chip to transfer the data to the controller, the data may be sensed out of the memory cells into page registers and then communicated to a conversion circuit, such as a serializer/deserializer (SerDes), via an internal data bus. The conversion circuit may convert the data it receives from the page registers via the internal data bus into a format that is suitable for transmission over the external data bus.
Size and layout requirements of the second chip may yield latencies and sampling window limitations. Such latencies and limitations may be tolerable under present operating read speeds, but prohibit increases. Thus, ways to reduce or eliminate the latencies and/or increase the data windows may be desirable so that increases in operating read speeds may be achieved.